2. How many times does the processor need to refer to memory when it fetches and executes an instruction that requires computation of a single operand, if the addressing mode used is 1) indirect, 2) PC-relative.
3. A pipelined processor has a clock rate of 1GHz and executes a program with N instructions. The pipeline has five stages and instructions are issued at a rate of one per clock.
4. Explain the major characteristics common to all of RISC architectures.
5. Explain how CISC and RISC can reduce the program execution time(T) by managing which of Ic, CPI and τ