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디지털 논리회로 111 detection

저작시기 2009.10 |등록일 2017.05.30 한글파일한글 (hwp) | 9페이지 | 가격 1,000원

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본문내용

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity mealy is
Port(
m_clk : in STD_LOGIC;
m_reset : in std_logic;
m_input : in STD_LOGIC;
m_s : in STD_LOGIC;
m_output : out STD_LOGIC;
l_output : out STD_LOGIC_VECTOR (0 to 3)
);
end mealy;
architecture Behavioral of mealy is

component counter_mealy
Port (
m_clk : in STD_LOGIC;
m_reset : in STD_LOGIC;
m_input : in STD_LOGIC;
m_output : out STD_LOGIC_VECTOR (0 to 3)
);
end component;

type st_mealy is( a, b, c, d, e, f, g);
signal state : st_mealy;

signal s_input : std_logic;
signal n_output: std_logic;

begin
stage0: counter_mealy PORT MAP(m_clk,m_s,n_output,l_output);

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