소개글

ASIC실험 A+

목차

: Quartus를 이용한 16진 카운터의 FPGA 구현
: State Diagram
: Counter
: Flip-flop
: ALU
: odd parity checker
: BCD to 7-segment
: decoder
: full adder

본문내용

2. 실험내용

title 6주차: Combinational Logic: odd parity checker(실험보고서)

3. 설계방법
3-bit 데이터(S2, S1, S0)의 odd parity bit 발생기와 이를 수신한 패리티 검출기의 진리표

parity checker의 부울식

p <= not(s(0) xor s(1) xor s(2))
y <= s & p

4. VHDL 코딩

parity checker

library ieee;
use ieee.std_logic_1164.all;

entity Parity_checker is
port(s : in std_logic_vector(2 downto 0);
y : out std_logic_vector(3 downto 0));
end Parity_checker;

architecture dataflow_des of Parity_checker is
signal p : std_logic;
begin
p <= not(s(0) xor s(1) xor s(2));
y <= s & p ;
end dataflow_des;

parity checker 테스트 벤치

--********************************************************************
--* This automatically generated Test Bench template has been created*
--* By ACTIVE-HDL <TBgen v1.11>. Copyright (C) ALDEC Inc. *
--* *
--* This file was generated on: 오전 10:43, 02-04-19 *
--* Tested entity name: parity_checker *
--* File name contains tested entity: $DSN\src\paritychecker.vhd *
--********************************************************************

참고 자료

없음

압축파일 내 파일목록