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[공학기술]디지털 시스템 설계 8장 연습문제(일부)

저작시기 2007.01 |등록일 2007.06.11 한글파일한글 (hwp) | 4페이지 | 가격 3,500원

소개글

디지털 시스템 설계 8장 연습문제 입니다.PCS(충북대)교수님과목입니다.
VHDL 코드와 웨이브폼 포함

목차

P8.2 For the BCD up counter circuit shown in Figure 8.19, what happens if the output of the AND gate comparator is connected to the clear signal instead of to the Load signal? Will it produce the same waveform? Explain your observations.
P8.7 use the 4-bit binary up-down counter with parallel load to construct an up-down counter circuit that outputs the sequence
P8.10 What are the valid address ranges for the y5 and y7 lines in the following circuits of Figure P8.10?
P8.12 Design an 8M-byte memory using 2M×4-bit RAM chips. Label all of the signals clearly.
P8.4 Write the behavioral VHDL code for the BCD up-down counter.
P8.9 Write the structural VHDL code for the BCD up-down counter based on the circuit diagram shown in Figure 8.21 Use the 4-bit binary up-down counter VHDL code as a component.

본문내용

P8.2 For the BCD up counter circuit shown in Figure 8.19, what happens if the output of the AND gate comparator is connected to the clear signal instead of to the Load signal? Will it produce the same waveform? Explain your observations.
⇒ And gate를 clear signal에 연결하게 되면 count 를 시작한 회로가 ‘1001’이 됐을때 AND gate는 ‘1’이 되므로 clear signal

P8.7 use the 4-bit binary up-down counter with parallel load to construct an up-down counter circuit that outputs the sequence : 7, 12, 19, 36, 42, 58, 57, repeatedly
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