검색어 입력폼

# [공학기술]디지털 시스템 설계 4장 연습문제(일부)

저작시기 2007.01 |등록일 2007.06.11 한컴오피스 (hwp) | 4페이지 | 가격 3,500원

## 소개글

디지털 시스템 설계 4장 연습문제 입니다.PCS(충북대)교수님과목입니다.
VHDL 코드와 웨이브폼 포함

## 목차

P4.1 Convert the following numbers to 12-bit binary numbers using twos complement representation.
P4.2 Convert the following twos complement binary numbers to decimal, octal, and hexadecimal formats.
P4.8 Draw the complete 4-bit ALU circuit having the following operations Use K-maps to reduce all of the equations to standard form.
P4.16 Draw the circuit for the 4 to 16 decoder using only 2 to 4 decoders.
P4.25 Use one 8 to 1 multiplexer to implement the function:
P4.29 Draw the circuit for a 4-bit iterative comparator that tests for the greater - than - or - equal - to relationship
P4.30 Draw the circuit for a 4-bit shifter that realizes the following operation table.ㅍ
P4.3 Write the complete structural VHDL code for the full-adder circuit shown in figure 4.1(c)
P4.20 Write the behavioral VHDL code for the 8-to-3 priority encoder.

## 본문내용

P4.1 Convert the following numbers to 12-bit binary numbers using two`s complement representation.
(d) BC416 => 1011 1100 0100 => 0100 0011 1100 => -43C16
(e) -47210 => 000111011000 => 1110 0010 1000

P4.2 Convert the following two`s complement binary numbers to decimal, octal, and hexadecimal formats.
(d) 1101011001 => -16710 , -2478 , -A716
(e) 0110101100 => 59610 , 11248 , 25416

P4.8 Draw the complete 4-bit ALU circuit having the following operations Use K-maps to reduce all of the equations to standard form.