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[VHDL설계] VHDL 문제풀이와 출력그림(한학기분)

등록일 2004.03.31 한글파일한글 (hwp) | 15페이지 | 가격 1,000원

소개글

10개에 해당하는 레포트입니다.한학기분이였습니다.
10문제가 조금 넘습니다.
이번에 이책이 번역되어 나왔죠...열심히 하세요...^^즐

목차

1> BCD Priority Encoder
2> DMUX8 코드와 시뮬레이션
3> 8bit 비교기(Active Low)
4> Component를 이용하여 16bit adder의 설계
5> 7.26 12-bit D flip-flop with a clock common to all flip-flops, using MAX+PLUS II primitives.
6> --7.27 Write a VHDL file that creates a 12-bit D flip-flop using the LPM commonent lpm_ff.(This component is instantiated as a D flip-flop by defalt,The required LPM component port names are: data, clock, and q.)
7> --7.40 Write a VHDL file for a 12-bit D flip-flop that uses MAX+PLUSⅡ DFF primitives, similar to that in Problem 7.26. Include active-LOW asynchronous clear(CLRN) and preset(PRN) inputs. Create a simulation file to verify the operation of your design
8> --7.41 Write a VHDL file for a 12-bit D flip-flop with asynchronous preset and clear, using the LPM component lpm_ff, similar to that in Problem 7.27. Required ports: data clocks, aclr(asynchronous clear), aset(asynchronous set), and q. Ports aset and aclr are active-HIGH. Add two signals to the VHDL design to make them active-LOW. Create a simulation file to verify the operation of your design.
9> --9.18 Design a synchronous mod-10 counter, using positive edge-triggered JK flip-flop. Check that unused states properly enter the main sequence. Draw a state diagram showing the unused states.
10> --9.52 Write the code for a VHDL design entity that implements a 4-bit universal shift register with asynchronous clear.
Create a simulation that verifies the design function.

본문내용

Report 1 BCD Priority Encoder

1. WHEN ELSE 를 사용하여 엔코더를 구성

entity bcdpe is
port(
d: in bit_vector (9 downto 0);
y: out integer range 0 to 9);
end bcdpe;

architecture encoder of bcdpe is
begin
y<= 9 when d(9)='1'else
8 when d(8)='1'else
7 when d(7)='1'else
6 when d(6)='1'else
5 when d(5)='1'else
4 when d(4)='1'else
3 when d(3)='1'else
2 when d(2)='1'else
1 when d(1)='1'else
0;
end encoder;

참고 자료

Digital Design with CPLD Application and VHDL
저자_Dueck
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