목차

*Introduction to VHDL
1.A First Example
2.Basic Building Blocks of VHDL Descriptions
3.Structural Description in VHDL
4.Data Flow Description in VHDL
5.Behavioral Description in VHDL
*Styles of Description
*The Design Entity Concept

본문내용

***Why is High-Level Simulation Required
Faster time-to-market
- Reduced prototype return
- Less time in the lab
- Verify design before board layout
- Verify ASICs and programmable logic before fabrication
- Develop software before PCB(printed Circuit Board)
Improve product quality
- Fewer cuts and jumpers on board
- Discover errors in lab ? not in the field
- Better price/performance
- Challenge higher clock rates and more complex Asics

참고 자료

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